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Design techniques for low-voltage and low-power analog-to-digital converters

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dc.contributor Moon, Un-Ku
dc.contributor Temes, Gabor
dc.contributor Mayaram, Karti
dc.contributor Liu, Huaping
dc.contributor Baker, Greg
dc.date 2005-10-18T17:17:11Z
dc.date 2005-10-18T17:17:11Z
dc.date 2005-09-15
dc.date 2005-10-18T17:17:11Z
dc.date.accessioned 2013-10-16T07:27:36Z
dc.date.available 2013-10-16T07:27:36Z
dc.date.issued 2013-10-16
dc.identifier http://hdl.handle.net/1957/514
dc.identifier.uri http://koha.mediu.edu.my:8181/xmlui/handle/1957/514
dc.description Graduation date: 2006
dc.description With the ever-increasing demand for portable devices used in applications such as wireless communication, mobile computing, consumer electronics, etc., the scaling of the CMOS process to deep submicron dimensions becomes more important to achieve low-cost, low-power and high-performance digital systems. However, this downscaling also requires similar shrinking of the supply voltage to insure device reliability. Even though the largest amount of signal processing is done in the digital domain, the on-chip analog-to-digital interface circuitry (analog-to-digital and digital-to-analog converters) is an important functional block in the system. These converters are also required to operate with low-voltage supply. In this thesis, design techniques for low-voltage and low-power analog-to-digital converters are proposed. The specific research contributions of this work include (1) introduction of a new low-voltage switching technique for switched- capacitor circuit design, (2) development of low-voltage and low-distortion delta- sigma modulator, (3) development of low-voltage switched-capacitor multiplying digital-to-analog converter (MDAC), (4) a new architecture for the low-power Nyquist rate pipelined ADC design. These design techniques enable the implementation of low-voltage and low-power CMOS analog-to-digital converters. To demonstrate the proposed design techniques, a 0.6 V, 82 dB, 2-2 cascaded audio delta-sigma ADC, a 0.9 V, 10-bit, 20MS/s CMOS pipelined ADC and a 2.4 V, 12-bit, 10MS/s CMOS pipelined ADC were implemented in standard CMOS processes.
dc.language en_US
dc.subject ADC
dc.subject low-voltage
dc.subject low-power
dc.subject switched-RC
dc.subject delta-sigma
dc.title Design techniques for low-voltage and low-power analog-to-digital converters
dc.type Thesis

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