A MOSCAP pipeline pseudo passive DAC

dc.contributor	Temes, Gabor C
dc.contributor	Settaluri, Raghu
dc.contributor	Traylor, Roger
dc.contributor	Kimura, Shoichi
dc.date	2005-09-21T18:27:23Z
dc.date	2005-09-21T18:27:23Z
dc.date	2005-09-15
dc.date	2005-09-21T18:27:23Z
dc.date.accessioned	2013-10-16T07:27:16Z
dc.date.available	2013-10-16T07:27:16Z
dc.date.issued	2013-10-16
dc.identifier	http://hdl.handle.net/1957/465
dc.identifier.uri	http://koha.mediu.edu.my:8181/xmlui/handle/1957/465
dc.description	Graduation date: 2006
dc.description	The design of a 10-bit pipelined charge redistribution DAC employing MOSCAPs biased in their accumulation mode is presented in this thesis. A switched capacitor filter and output buffer have also been designed for the system. The effect of MOSCAP nonlinearity on the performance of the pipelined charge redistribution DAC has been analyzed. MOS capacitors and their models available for simulation have been discussed. In addition, the effect of more general capacitor nonlinearities on the performance of the DAC has been presented.
dc.language	en_US
dc.subject	DAC
dc.subject	pipeline
dc.subject	MOSCAP
dc.subject	digital-to-analog
dc.subject	SCF
dc.subject	D/A
dc.title	A MOSCAP pipeline pseudo passive DAC
dc.type	Thesis

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