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Design techniques for PVT tolerant phase-locked loops

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dc.contributor Moon, Un-Ku
dc.contributor Mayaram, Kartikeya
dc.contributor Temes, Gabor
dc.contributor Wang, Zhongfeng
dc.contributor Hanumolu, Pavan
dc.date 2007-01-29T18:42:56Z
dc.date 2007-01-29T18:42:56Z
dc.date 2007-01-04
dc.date 2007-01-29T18:42:56Z
dc.date.accessioned 2013-10-16T07:44:10Z
dc.date.available 2013-10-16T07:44:10Z
dc.date.issued 2013-10-16
dc.identifier http://hdl.handle.net/1957/3866
dc.identifier.uri http://koha.mediu.edu.my:8181/xmlui/handle/1957/3866
dc.description Graduation date: 2007
dc.description The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs that are susceptible to process, voltage, and temperature (PVT) variations are dramatically affected. To truly benefit from process scaling, PVT tolerant designs of high-performance PLLs are essential. In this dissertation, circuit techniques that can mitigate the impacts of PVT variations on PLL performance are presented. In the context of ring voltage-controlled oscillator (VCO) based PLLs, an on-chip calibration technique for reducing the supply voltage sensitivity is described. This method rejects supply noise while avoiding the use of supply regulation, which makes it more desirable in the design of low-voltage high-performance ring VCOs. In a wide-tuning range LC-VCO based PLL frequency synthesizer, design techniques for maintaining a constant loop bandwidth are presented. Having a constant loop bandwidth that is insensitive to PVT variations helps PLL frequency synthesizers to achieve optimum performance in all frequency bands. The proposed circuit techniques are validated by measurement results obtained from prototype chips. The concepts that have been presented in the context of analog PLL implementations can be easily migrated to digital PLLs.
dc.language en_US
dc.subject phase-locked loop
dc.subject frequency synthesizer
dc.subject voltage controlled oscillator
dc.subject calibration
dc.title Design techniques for PVT tolerant phase-locked loops
dc.type Thesis

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