| dc.contributor |
Mayaram, Kartikeya |
|
| dc.contributor |
Moon, Un-Ku |
|
| dc.contributor |
Yang, Jimmy |
|
| dc.contributor |
Traylor, Roger |
|
| dc.contributor |
Mikulchenko, Oleg |
|
| dc.contributor |
Hanumolu, Pavan Kumar |
|
| dc.date |
2007-01-18T16:07:42Z |
|
| dc.date |
2007-01-18T16:07:42Z |
|
| dc.date |
2006-12-12 |
|
| dc.date |
2007-01-18T16:07:42Z |
|
| dc.date.accessioned |
2013-10-16T07:43:55Z |
|
| dc.date.available |
2013-10-16T07:43:55Z |
|
| dc.date.issued |
2013-10-16 |
|
| dc.identifier |
http://hdl.handle.net/1957/3804 |
|
| dc.identifier.uri |
http://koha.mediu.edu.my:8181/xmlui/handle/1957/3804 |
|
| dc.description |
Graduation date: 2007 |
|
| dc.description |
A digital implementation of a PLL has several advantages compared to its
analog counterpart. These include easy scalability with process shrink, elimination
of the noise susceptible analog control for a voltage controlled oscillator (VCO) and
the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL)
implementations have achieved performance similar to that of analog PLLs. However,
there is an upper bound on the bandwidth of a DPLL and this limits its
capability to track an input signal. The research described in this thesis is focused
on new digital PLL architectures that overcome this bandwidth limitation in linear
as well as in digital PLLs.
A systematic design procedure for a second-order digital phase-locked loop
with a linear phase detector is proposed. The design procedure is based on the
analogy between a type-II second-order analog PLL and a digital PLL. A new
digital PLL architecture featuring a linear phase detector which eliminates the
noise-bandwidth tradeoff is presented. It employs a stochastic time-to-digital converter
(STDC) and a high frequency delta-sigma dithering to achieve a wide PLL
bandwidth and a low jitter. The measured results obtained from the prototype
chip demonstrate a significant jitter improvement with the STDC.
A bang-bang digital PLL employing an adaptive tracking technique and a
novel frequency acquisition scheme achieves a wide tracking range and fast frequency
acquisition. The DPLL operates over a wide frequency range from 0.6GHz
to 2GHz. The adaptive tracking mechanism detects PLL slewing by monitoring
the output of the binary phase detector and corrects the VCO frequency to
prevent loss of lock. The experimental results illustrate a tracking bandwidth improvement
of 100%. As a result, this DPLL is suitable for applications employing
spread-spectrum clocking. A fast frequency lock is achieved with a novel frequency
detector which extracts the frequency error from the feedback divider in a PLL. |
|
| dc.language |
en_US |
|
| dc.subject |
digital phase-locked loop |
|
| dc.title |
Digital phase-locked loops for multi-GHz clock generation |
|
| dc.type |
Thesis |
|