| dc.description |
Scaling of CMOS technology has progressed relentlessly for the past several
decades. In order for this unprecedented scaling to benefit the performance of
large digital systems, the communication bandwidth between integrated circuits
(ICs) must scale accordingly. However, interconnect technology does not scale as
aggressively, making communication between chips the major bottleneck in overall
system performance. In addition, supply voltage scaling, increasing device leakage,
and increased noise make existing signaling circuits inefficient and difficult to scale.
In this thesis, both analog and digital enhancement techniques to mitigate
scaling related issues and improve the performance of building blocks used in high-
speed signaling systems are discussed. A digital-to-phase converter (DPC) with a
resolution better than 100 femto-second resolution, a hybrid analog/digital clock
and data recovery (CDR) architecture that improves the tracking range of tra-
ditional CDRs by an order of magnitude, and a digital CDR architecture that
obviates the need for the charge pump and the large area occupying loop filter,
while achieving error-free operation are presented. Measured results obtained from
the prototype chips are presented to illustrate the proposed design techniques. |
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