Date presented: 2006-07-21
Graduation date: 2007
A digital phase locked loop (DPLL) and a statistical time-to-digital
converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI
CMOS process. This work summarizes these designs and characterizes the
measured performance. Simulations supplement the measurements where
applicable.
The DPLL was found to reach a locked state under a limited range of
input conditions. Evaluation of the DPLL's digitally controlled analog
oscillator (DCAO) revealed that transistor mismatch resulted in a
non-ideal tuning curve. Simulations and measurements of the DCAO phase
noise showed good correlation.
The STDC circuit was characterized for several test chips. Measurement
results show good matching between the chips for the same input
conditions. The ability to achieve higher resolution than standard
time-to-digital converters is demonstrated through simulations and
measurements.