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Incremental Verification of Timing Constraints for Real-Time Systems

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dc.creator Andrei, Å tefan
dc.creator Chin, Wei Ngan
dc.creator Rinard, Martin C.
dc.date 2004-12-13T06:50:40Z
dc.date 2004-12-13T06:50:40Z
dc.date 2005-01
dc.date.accessioned 2013-10-09T02:49:28Z
dc.date.available 2013-10-09T02:49:28Z
dc.date.issued 2013-10-09
dc.identifier http://hdl.handle.net/1721.1/7421
dc.identifier.uri http://koha.mediu.edu.my:8181/xmlui/handle/1721
dc.description Testing constraints for real-time systems are usually verified through the satisfiability of propositional formulae. In this paper, we propose an alternative where the verification of timing constraints can be done by counting the number of truth assignments instead of boolean satisfiability. This number can also tell us how “far away” is a given specification from satisfying its safety assertion. Furthermore, specifications and safety assertions are often modified in an incremental fashion, where problematic bugs are fixed one at a time. To support this development, we propose an incremental algorithm for counting satisfiability. Our proposed incremental algorithm is optimal as no unnecessary nodes are created during each counting. This works for the class of path RTL. To illustrate this application, we show how incremental satisfiability counting can be applied to a well-known rail-road crossing example, particularly when its specification is still being refined.
dc.description Singapore-MIT Alliance (SMA)
dc.format 148308 bytes
dc.format application/pdf
dc.language en
dc.relation Computer Science (CS);
dc.subject Real-time infrastructure and development
dc.subject timing constraint
dc.subject #SAT problem
dc.subject incremental computation
dc.title Incremental Verification of Timing Constraints for Real-Time Systems
dc.type Article

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