| dc.creator |
Leong, Hoi Liong |
|
| dc.creator |
Gan, C.L. |
|
| dc.creator |
Pey, Kin Leong |
|
| dc.creator |
Tsang, Chi-fo |
|
| dc.creator |
Thompson, Carl V. |
|
| dc.creator |
Hongyu, Li |
|
| dc.date |
2004-12-10T14:24:14Z |
|
| dc.date |
2004-12-10T14:24:14Z |
|
| dc.date |
2005-01 |
|
| dc.date.accessioned |
2013-10-09T02:49:26Z |
|
| dc.date.available |
2013-10-09T02:49:26Z |
|
| dc.date.issued |
2013-10-09 |
|
| dc.identifier |
http://hdl.handle.net/1721.1/7372 |
|
| dc.identifier.uri |
http://koha.mediu.edu.my:8181/xmlui/handle/1721 |
|
| dc.description |
Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures were created by thermocompression bonding and the bond toughness was measured using the four-point test. The effects of bonding temperature, physical bonding and failure mechanisms were investigated. The surface effects on copper surface due to pre-bond clean (with glacial acetic acid) were also looked into. A maximum average bond toughness of approximately 35 J/m² was obtained bonding temperature 300 C. |
|
| dc.description |
Singapore-MIT Alliance (SMA) |
|
| dc.format |
11870 bytes |
|
| dc.format |
application/pdf |
|
| dc.language |
en |
|
| dc.relation |
Advanced Materials for Micro- and Nano-Systems (AMMNS); |
|
| dc.subject |
three dimensional integrated circuits |
|
| dc.subject |
bonded copper interconnects |
|
| dc.subject |
bonding |
|
| dc.subject |
fabrication |
|
| dc.title |
Preliminary Characterisation of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits |
|
| dc.type |
Article |
|