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Efficient verification of VLSI circuits based on syntax and denotational semantics

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dc.contributor Aelten, Filip Van.
dc.date 2004-03-02T18:50:47Z
dc.date 2004-03-02T18:50:47Z
dc.date 1989
dc.date.accessioned 2013-10-09T02:34:28Z
dc.date.available 2013-10-09T02:34:28Z
dc.date.issued 2013-10-09
dc.identifier no. 546
dc.identifier http://hdl.handle.net/1721.1/4206
dc.identifier.uri http://koha.mediu.edu.my:8181/xmlui/handle/1721
dc.description Filip Van Aelten.
dc.description Also issued as: Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.
dc.description Includes bibliographical references (p. 139-141).
dc.description Support provided by Analog Devices.
dc.format 141 p.
dc.format 7071957 bytes
dc.format application/pdf
dc.language eng
dc.publisher Research Laboratory of Electronics, Massachusetts Institute of Technology
dc.relation Technical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 546.
dc.subject TK7855.M41 R43 no.546
dc.title Efficient verification of VLSI circuits based on syntax and denotational semantics


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