This paper presents an efficient method to design cascaded ΣΔ modulators implemented with continuous-time circuits. Instead of using a discrete-to-continuous time transformation, the proposed methodology is based on the direct synthesis of the whole cascaded architecture. This leads to more efficient topologies in terms of circuit complexity, power consumption and robustness with respect to parasitics. As an application, new cascaded topologies are synthesized and optimized to cope with VDSL specifications.This work has been supported by the Spanish CICYT Project TIC2001-0929/ADAVERE.Peer reviewed