This paper presents a toolbox for the time-domain simulation and optimization-based high-level synthesis of pipeline analog-to-digital converters in MATLAB®. Behavioral models of building blocks, including their critical error mechanisms, are described and incorporated into SIMULINK® as C-compiled S-functions. This approach significantly speeds up system-level simulations while keeping high accuracy −verified with HSPICE− and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable alternative for the design of broadband communication analog front-ends. As a case study, an embedded 0.13μm CMOS 12bit@80MS/s ADC for a PLC chipset is designed to show the capabilities of the presented tool.This work has been supported by the MEDEA+ (A110 MIDAS) Project.Peer reviewed