This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, or 4-bit internal resolution. The modulator is implemented with fully-differential switched capacitor circuits in a CMOS 0.35-um digital technology. The estimated power consumption is 78mW, from a 3.3-V supply.This work has been partially supported by the ESPRIT Project 29261 and the CICYT Project TIC 97-0580.Peer reviewed