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A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator

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dc.creator Tortosa, Ramón
dc.creator Aceituno, Antonio
dc.creator Rosa, José M. de la
dc.creator Rodríguez-Vázquez, Ángel
dc.creator Fernández, Francisco V.
dc.date 2008-04-28T15:10:20Z
dc.date 2008-04-28T15:10:20Z
dc.date 2007-05
dc.date.accessioned 2017-01-31T01:05:19Z
dc.date.available 2017-01-31T01:05:19Z
dc.identifier R. Tortosa-Navas,A. Aceituno, J. M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: "A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator". Proceeding of the 2007 International Symposium on Circuits and Systems (ISCAS), New Orleans, May 2007.
dc.identifier 1-4244-0921-7/07
dc.identifier http://hdl.handle.net/10261/3829
dc.identifier.uri http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3829
dc.description This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.
dc.description This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC.
dc.description Peer reviewed
dc.format 653200 bytes
dc.format application/pdf
dc.language eng
dc.publisher Institute of Electrical and Electronics Engineers
dc.rights openAccess
dc.subject Continuous-Time Circuits
dc.subject Sigma-Delta Modulators
dc.title A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator
dc.type Artículo


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