This paper presents a MATLAB® toolbox for the time-domain simulation and high-level sizing of pipeline analog-to-digital converters. SIMULINK® C-coded S-functions are used to describe the behavioral models of all building blocks, including their main circuit errors. This approach significantly speeds up system-level simulations while keeping high accuracy −verified with HSPICE− and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable CAD tool for the high-level design of broadband communication analog front-ends. As a case study, an embedded 0.13μm CMOS 12bit@80MS/s A/D interface for a PLC chipset is designed to show the capabilities of the presented tool.This work has been supported by the MEDEA+ (A110 MIDAS) Project.Peer reviewed