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A 0.35μm CMOS 17-bit@40kS/s Sensor A/D Interface Based on a Programmable-Gain Cascade 2-1 ΣΔ Modulator

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dc.creator García-González, José Manuel
dc.creator Escalera, Sara
dc.creator Rosa, José M. de la
dc.creator Guerra, Oscar
dc.creator Medeiro, Fernando
dc.creator Río, Rocío del
dc.creator Pérez-Verdú, Belén
dc.creator Rodríguez-Vázquez, Ángel
dc.date 2008-04-28T11:05:46Z
dc.date 2008-04-28T11:05:46Z
dc.date 2004-05
dc.date.accessioned 2017-01-31T01:04:35Z
dc.date.available 2017-01-31T01:04:35Z
dc.identifier S. Escalera, J.M. García-González, J.M. de la Rosa, O. Guerra, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez: "A 0.35μm CMOS 17-bit@40kS/s Sensor A/D Interface Based on a Programmable-Gain Cascade 2-1 ΣΔ Modulator". Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS), pp. I.205-I.208, Vancouver, May 2004.
dc.identifier 0-7803-8251-X/04
dc.identifier http://hdl.handle.net/10261/3791
dc.identifier.uri http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3791
dc.description This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35μm standard CMOS technology. The circuit is composed of a low-noise instrumentation preamplifier and a SC cascade (2-1) ΣΔ modulator. The preamplifier, based on hybrid Nested-Miller compensated four-stage opamps, has a fixed gain of 10 and it is capable of handling signals with 20kHz-bandwidth and amplitudes ranging from μVs to hundreds of mVs with a signal-to-(noise+distortion) ratio over 100dB. The modulator architecture has a programmable gain for a better fitting to the characteristics of different sensor outputs. The design of both circuits is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the interface hierarchy. Simulation results show 17-bit@40kS/s for all cases of the modulator gain.
dc.description EU ESPRIT IST Project 2001-34283/TAMES-2 Spanish CICYT Project TIC2001-0929/ADAVERE.
dc.description Peer reviewed
dc.format 376211 bytes
dc.format application/pdf
dc.language eng
dc.publisher Institute of Electrical and Electronics Engineers
dc.rights openAccess
dc.subject Sigma-Delta Modulator
dc.subject Automotive
dc.subject Sensor Interface
dc.subject Analog-to-Digital Converters
dc.title A 0.35μm CMOS 17-bit@40kS/s Sensor A/D Interface Based on a Programmable-Gain Cascade 2-1 ΣΔ Modulator
dc.type Artículo


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