| dc.creator |
Río, Rocío del |
|
| dc.creator |
Rosa, José M. de la |
|
| dc.creator |
Medeiro, Fernando |
|
| dc.creator |
Pérez-Verdú, Belén |
|
| dc.creator |
Rodríguez-Vázquez, Ángel |
|
| dc.date |
2008-04-28T05:37:33Z |
|
| dc.date |
2008-04-28T05:37:33Z |
|
| dc.date |
2001-09 |
|
| dc.date.accessioned |
2017-01-31T01:04:14Z |
|
| dc.date.available |
2017-01-31T01:04:14Z |
|
| dc.identifier |
The 8th IEEE International Conference on Electronics, Circuits and Systems 1: 501-504 (2001) |
|
| dc.identifier |
0-7803-7057-0 |
|
| dc.identifier |
http://hdl.handle.net/10261/3768 |
|
| dc.identifier |
10.1109/ICECS.2001.957788 |
|
| dc.identifier.uri |
http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3768 |
|
| dc.description |
Comunicación presentada al "ICECS 2001" celebrado del 2 al 5 de Septiembre del 2001 en Malta. |
|
| dc.description |
We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use only 16 oversampling ratio. Especial emphasis is placed on technology issues, namely: poor analog performance and substrate coupling. The
measured performances are 13-bit dynamic range operating at 2MS/s and 12-bit dynamic range operating at 4MS/s. The modulator consumes 77mW from a 3.3-V supply and occupies 1.32 mm2. |
|
| dc.description |
This work has been supported by the ESPRIT Project 29261 MIXMODEST. |
|
| dc.description |
Peer reviewed |
|
| dc.format |
453788 bytes |
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| dc.format |
application/pdf |
|
| dc.language |
eng |
|
| dc.publisher |
Institute of Electrical and Electronics Engineers |
|
| dc.relation |
http://dx.doi.org/10.1109/ICECS.2001.957788 |
|
| dc.rights |
openAccess |
|
| dc.subject |
Analog-to-digital converters |
|
| dc.subject |
ADSL application |
|
| dc.title |
High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology |
|
| dc.type |
Comunicación de congreso |
|