Sigma-delta converters are very well suited for the implementation of analog front-ends in CMOS SoCs. Owing to different advances on both architectures and circuit techniques, these converters are today employed for applications spanning a very wide frequency interval, from instrumentation to telecom. They are clearly dominant in measurement, voice, and audio systems, and coexist with algorithmic, subranging, and pipeline converters in systems for mobile communications and broadband wireline applications like ADSL. Furthermore, it is commonly accepted that whenever an industrial application can be addressed by using a ΣΔ converter, this solution is considered very well suited, for feasibility, yield, robustness, and time-to-market reasons.During the last few years, significant efforts and contributions have been made to decrease the power budget of sigma-delta converters, to increase their bandwidth and to make them fully compatible with last generation, low-voltage sub-micron technologies. The extended usage of multi-bit quantizers, the emergence of new continuous-time architectures and synthesis techniques, the combination of continuous-time and discrete-time filters, the usage of calibration, the compatibility with very low voltage supplies,... are examples of recent advances on CMOS sigma-delta converter design.Based on a comprehensive description of sigma-delta operating principles, this tutorial presents an overview of the advances which are currently shaping the field of CMOS sigma-delta converter design. Topics covered in the tutorial include the following: New architectures and optimization techniques for wideband discrete-time sigma-delta modulators. New synthesis techniques and architectures for continuous-time sigma-delta modulators. Continuous-time, discrete-time hybrid architectures. New sigma-delta and hybrid converter architecture: parallel, time-interleaved, sigma-delta pipeline,... Calibration techniques. Strategies for multi-mode and multi-standard transceivers. Low-voltage, low-power design. Deep-submicron design.Peer reviewed