| dc.creator |
Domínguez-Castro, R. |
|
| dc.creator |
Rodríguez-Vázquez, Ángel |
|
| dc.creator |
Rosa, José M. de la |
|
| dc.creator |
Delgado-Restituto, Manuel |
|
| dc.creator |
Medeiro, Fernando |
|
| dc.date |
2008-04-26T23:48:23Z |
|
| dc.date |
2008-04-26T23:48:23Z |
|
| dc.date |
2003 |
|
| dc.date.accessioned |
2017-01-31T01:03:54Z |
|
| dc.date.available |
2017-01-31T01:03:54Z |
|
| dc.identifier |
1-4020-7546-4 |
|
| dc.identifier |
http://hdl.handle.net/10261/3751 |
|
| dc.identifier.uri |
http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3751 |
|
| dc.description |
This chapter first presents an overview of CMOS voltage comparator architectures and circuits. Starting from the identification of the comparator behavior, Section 2 introduces several comparator architectures and circuits. Then, Section 3 assumes these topologies, characterizes high-level attributes, such as static gain, unitary time constant, etc., and analyzes the trade-off for each architecture. Such analysis provides a basis for comparison among architectures. These previous sections of the chapter neglect the influence of circuit dissymmetries. Dissymmetries are covered in Section 4; and new comparator topologies are
presented to overcome the offset caused by dissymmetries. Related high-level trade-offs for these topologies are also studied in this section. |
|
| dc.description |
This work has been partially supported by the spanish MCyT and the ERDF - Project TIC2001-0929 (ADAVERE), and the European Union Project IST-
2001-34283 (TAMES). The useful comments from Dr. Gustavo Liñán are highly appreciated. |
|
| dc.description |
Peer reviewed |
|
| dc.format |
863347 bytes |
|
| dc.format |
application/pdf |
|
| dc.language |
eng |
|
| dc.publisher |
Springer |
|
| dc.relation |
http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4020-7546-9 |
|
| dc.rights |
closedAccess |
|
| dc.subject |
CMOS Comparators |
|
| dc.title |
CMOS Comparators |
|
| dc.type |
Capítulo de libro |
|