El pdf del artículo es la versión post-print.This paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16.4 bit at a digital output rate of 9.6 kHz with a power consumption of 1.7 mW. It yields a value of Power(W)/[2^resolution(bit) * Outpur rate(Hz)] which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable ΣΔMs using CAD methodologies.Peer reviewed