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Fourth-order cascade SC ΣΔ modulators: a comparative study

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dc.creator Medeiro, Fernando
dc.creator Pérez-Verdú, Belén
dc.creator Rosa, José M. de la
dc.creator Rodríguez-Vázquez, Ángel
dc.date 2008-04-24T14:03:02Z
dc.date 2008-04-24T14:03:02Z
dc.date 1998-10-01
dc.date.accessioned 2017-01-31T01:03:36Z
dc.date.available 2017-01-31T01:03:36Z
dc.identifier IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications: 1041-1051 (1998)
dc.identifier 1057-7122
dc.identifier http://hdl.handle.net/10261/3729
dc.identifier 10.1109/81.728858
dc.identifier.uri http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3729
dc.description Fourth-order cascade ΣΔ modulators are very well suited for IC implementation using analog sampled-data circuits because of their robust, stable operation and their capability to achieve high resolution and wide bandwidth with moderate power consumption. However, their optimum realization requires careful consideration of their performance degradations due to the hardware nonidealities. This paper presents a comparative study of the influence of finite op-amp gain and capacitor mismatch on the performance of fourth-order cascade ΣΔ modulators realized by means of switched-capacitor circuits. It considers single-bit and multibit quantizers and draws a number of comparative remarks validated by time-domain behavioral simulations.
dc.description This work was supported in part by the CEE ESPRIT Program under Project #8795 (AMFIS).
dc.description Peer reviewed
dc.format 397876 bytes
dc.format application/pdf
dc.language eng
dc.publisher Institute of Electrical and Electronics Engineers
dc.relation http://dx.doi.org/10.1109/81.728858
dc.rights openAccess
dc.subject Analog-digital conversion
dc.subject ΣΔ modulators
dc.subject Switched-capacitor circuits
dc.title Fourth-order cascade SC ΣΔ modulators: a comparative study
dc.type Artículo


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