| dc.creator |
Río, Rocío del |
|
| dc.creator |
Medeiro, Fernando |
|
| dc.creator |
Pérez-Verdú, Belén |
|
| dc.creator |
Rodríguez-Vázquez, Ángel |
|
| dc.date |
2008-04-15T17:28:46Z |
|
| dc.date |
2008-04-15T17:28:46Z |
|
| dc.date |
1998-11 |
|
| dc.date.accessioned |
2017-01-31T01:02:22Z |
|
| dc.date.available |
2017-01-31T01:02:22Z |
|
| dc.identifier |
Proc. Design of Circuits and Integrated Systems Conf. (DCIS’98), pp. 76-81, Madrid, November 1998. |
|
| dc.identifier |
http://hdl.handle.net/10261/3598 |
|
| dc.identifier.uri |
http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3598 |
|
| dc.description |
The use of Sigma-Delta (ΣΔ) modulation for analog-to-digital conversion (ADC) in the
communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at 4Msample/s Nyquist rate using very low oversampling ratio. They show very low sensitivity to the internal D-to-A conversion (DAC) error with no calibration required. Simulations show that such performance can be achieved even in presence of circuit imperfections. |
|
| dc.description |
This work has been partially supported by the Spanish CICYT Project TIC 97-0580. |
|
| dc.description |
Peer reviewed |
|
| dc.format |
118489 bytes |
|
| dc.format |
application/pdf |
|
| dc.language |
eng |
|
| dc.publisher |
Universidad Carlos III de Madrid |
|
| dc.rights |
openAccess |
|
| dc.subject |
ΣΔ Modulator |
|
| dc.subject |
A/D Conversion |
|
| dc.subject |
Communication Frequency Range |
|
| dc.title |
High-Order Cascade Multi-bit ΣΔ Modulators for High-Speed A/D Conversion |
|
| dc.type |
Comunicación de congreso |
|