| dc.creator |
Baturone, I. |
|
| dc.creator |
Sánchez-Solano, Santiago |
|
| dc.creator |
Huertas-Díaz, J. L. |
|
| dc.date |
2008-04-10T17:06:53Z |
|
| dc.date |
2008-04-10T17:06:53Z |
|
| dc.date |
2000-06 |
|
| dc.date.accessioned |
2017-01-31T01:01:59Z |
|
| dc.date.available |
2017-01-31T01:01:59Z |
|
| dc.identifier |
Analog Integrated Circuits and Signal Processing 23(3): 199-210 (2000) |
|
| dc.identifier |
0925-1030 (Print) |
|
| dc.identifier |
1573-1979 (Online) |
|
| dc.identifier |
http://hdl.handle.net/10261/3530 |
|
| dc.identifier |
10.1023/A:1008367503866 |
|
| dc.identifier.uri |
http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3530 |
|
| dc.description |
El pdf del artículo es la versión de autor. |
|
| dc.description |
Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design based on current-mode data converters is presented herein. Continuous-time algorithmic converters are chosen to reduce the control circuitry and to obtain a modular design based on a cascade of bit cells. Several circuit structures to implement these cells are presented and discussed. The one that is selected enables a better trade-off speed/power than others previously reported in the literature while maintaining a low area occupation. The resulting multiplier/divider circuit offers a low voltage operation, provides the division result in both analog and digital formats, and it is suitable for applications of low or middle resolution (up to 9 bits) like applications to fuzzy controllers. The analysis is illustrated with Hspice simulations and experimental results from a CMOS multiplier/divider prototype with 5-bit resolution. Experimental results from a CMOS current-mode fuzzy controller chip that contains the proposed design are also included. |
|
| dc.description |
We gratefully acknowledge support from C.S.I.C (Consejo Superior de Investigaciones
Científicas) under a postdoctoral grant of the first author. |
|
| dc.description |
Peer reviewed |
|
| dc.format |
223300 bytes |
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| dc.format |
application/pdf |
|
| dc.language |
eng |
|
| dc.publisher |
Springer |
|
| dc.relation |
http://dx.doi.org/10.1023/A:1008367503866 |
|
| dc.rights |
openAccess |
|
| dc.subject |
CMOS multiplier/divider circuits |
|
| dc.subject |
Current-mode signal processing |
|
| dc.subject |
Continuous-time data converters |
|
| dc.subject |
Fuzzy logic hardware |
|
| dc.title |
CMOS design of a current-mode multiplier/divider circuit with applications to fuzzy controllers |
|
| dc.type |
Artículo |
|