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Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/6807
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dc.creatorKeckler, Stephen W.-
dc.date2004-10-20T19:57:35Z-
dc.date2004-10-20T19:57:35Z-
dc.date1992-09-01-
dc.date.accessioned2013-10-09T02:46:59Z-
dc.date.available2013-10-09T02:46:59Z-
dc.date.issued2013-10-09-
dc.identifierAITR-1355-
dc.identifierhttp://hdl.handle.net/1721.1/6807-
dc.identifier.urihttp://koha.mediu.edu.my:8181/xmlui/handle/1721-
dc.descriptionThis report describes Processor Coupling, a mechanism for controlling multiple ALUs on a single integrated circuit to exploit both instruction-level and inter-thread parallelism. A compiler statically schedules individual threads to discover available intra-thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle byscycle basis, and several threads can be active concurrently. Simulation results show that Processor Coupling performs well both on single threaded and multi-threaded applications. The experiments address the effects of memory latencies, function unit latencies, and communication bandwidth between function units.-
dc.format165 p.-
dc.format19986107 bytes-
dc.format16194697 bytes-
dc.formatapplication/postscript-
dc.formatapplication/pdf-
dc.languageen_US-
dc.relationAITR-1355-
dc.subjectruntime scheduling-
dc.subjectcompile time scheduling-
dc.subjectparallelscomputers-
dc.subjectmultithreading-
dc.titleA Coupled Multi-ALU Processing Node for a Highly Parallel Computer-
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