Generating efficient layouts from optimized MOS circuit schematics

Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/4957

Full metadata record

DC Field	Value	Language
dc.contributor	Baltus, Donald George.	-
dc.date	2004-03-03T22:15:29Z	-
dc.date	2004-03-03T22:15:29Z	-
dc.date	1988	-
dc.date.accessioned	2013-10-09T02:36:58Z	-
dc.date.available	2013-10-09T02:36:58Z	-
dc.date.issued	2013-10-09	-
dc.identifier	no. 535	-
dc.identifier	http://hdl.handle.net/1721.1/4957	-
dc.identifier.uri	http://koha.mediu.edu.my:8181/xmlui/handle/1721	-
dc.description	Donald George Baltus.	-
dc.description	Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.	-
dc.description	Includes bibliographical references.	-
dc.description	Supported by the U.S. Air Force--Office of Scientific Research. AFOSR-86-0164 Supported in part by a National Science Foundation Graduate Fellowship. Supported in part by Thinking Machines Corporation. 2305/B4	-
dc.format	ix, 194 p.	-
dc.format	10316361 bytes	-
dc.format	application/pdf	-
dc.language	eng	-
dc.publisher	Research Laboratory of Electronics, Massachusetts Institute of Technology	-
dc.relation	Technical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 535.	-
dc.subject	TK7855.M41 R43 no.535	-
dc.title	Generating efficient layouts from optimized MOS circuit schematics	-
Appears in Collections:	MIT Items

Files in This Item:

There are no files associated with this item.

DSpace JSPUI