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http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/4957| Title: | Generating efficient layouts from optimized MOS circuit schematics |
| Authors: | Baltus, Donald George. |
| Keywords: | TK7855.M41 R43 no.535 |
| Issue Date: | 9-Oct-2013 |
| Publisher: | Research Laboratory of Electronics, Massachusetts Institute of Technology |
| Description: | Donald George Baltus. Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988. Includes bibliographical references. Supported by the U.S. Air Force--Office of Scientific Research. AFOSR-86-0164 Supported in part by a National Science Foundation Graduate Fellowship. Supported in part by Thinking Machines Corporation. 2305/B4 |
| URI: | http://koha.mediu.edu.my:8181/xmlui/handle/1721 |
| Other Identifiers: | no. 535 http://hdl.handle.net/1721.1/4957 |
| Appears in Collections: | MIT Items |
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