Graph-based representations and coupled verification of VLSI schematics and layouts

Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/4205

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DC Field	Value	Language
dc.contributor	Bamji, Cyrus S.	-
dc.date	2004-03-02T18:30:24Z	-
dc.date	2004-03-02T18:30:24Z	-
dc.date	1989	-
dc.date.accessioned	2013-10-09T02:34:28Z	-
dc.date.available	2013-10-09T02:34:28Z	-
dc.date.issued	2013-10-09	-
dc.identifier	no. 547	-
dc.identifier	http://hdl.handle.net/1721.1/4205	-
dc.identifier.uri	http://koha.mediu.edu.my:8181/xmlui/handle/1721	-
dc.description	Cyrus S. Bamji.	-
dc.description	Includes bibliographical references (p. 199-202).	-
dc.description	Work supported by the Air Force Office of Scientific Research. AFSOR 86-0164 Work supported by IBM and Analog Devices.	-
dc.format	202 p.	-
dc.format	12241617 bytes	-
dc.format	application/pdf	-
dc.language	eng	-
dc.publisher	Research Laboratory of Electronics, Massachusetts Institute of Technology	-
dc.relation	Technical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 547.	-
dc.subject	TK7855.M41 R43 no.547	-
dc.title	Graph-based representations and coupled verification of VLSI schematics and layouts	-
Appears in Collections:	MIT Items

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