RM³ Processing for In-plane Optical Interconnects on Si-CMOS and the Impact of Topographic Features on Losses in Deposited Dielectric Waveguides

Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/1721.1/3963

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DC Field	Value	Language
dc.creator	Barkley, Edward	-
dc.creator	Fonstad, Clifton G. Jr.	-
dc.date	2003-12-20T17:27:58Z	-
dc.date	2003-12-20T17:27:58Z	-
dc.date	2004-01	-
dc.date.accessioned	2013-10-09T02:33:41Z	-
dc.date.available	2013-10-09T02:33:41Z	-
dc.date.issued	2013-10-09	-
dc.identifier	http://hdl.handle.net/1721.1/3963	-
dc.identifier.uri	http://koha.mediu.edu.my:8181/xmlui/handle/1721	-
dc.description	This paper describes recent progress in a continuing program to develop and apply RM³ (recess mounting with monolithic metallization) technologies for heterogeneous integration. Particular emphasis is placed on the applicability of RM³ integration to in-plane geometries for on-chip optical clock and signal distribution and on the suitability of commercially processed IC wafers for use as substrates for rectangular dielectric waveguides.	-
dc.description	Singapore-MIT Alliance (SMA)	-
dc.format	354502 bytes	-
dc.format	application/pdf	-
dc.language	en	-
dc.relation	Advanced Materials for Micro- and Nano-Systems (AMMNS);	-
dc.subject	optoelectronic integration	-
dc.subject	heterogeneous integration	-
dc.subject	hybrid assembly	-
dc.subject	in-plane laser diodes	-
dc.subject	rectangular dielectric waveguides	-
dc.title	RM³ Processing for In-plane Optical Interconnects on Si-CMOS and the Impact of Topographic Features on Losses in Deposited Dielectric Waveguides	-
dc.type	Article	-
Appears in Collections:	MIT Items

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