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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3768| Title: | High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology |
| Keywords: | Analog-to-digital converters ADSL application |
| Publisher: | Institute of Electrical and Electronics Engineers |
| Description: | Comunicación presentada al "ICECS 2001" celebrado del 2 al 5 de Septiembre del 2001 en Malta. We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use only 16 oversampling ratio. Especial emphasis is placed on technology issues, namely: poor analog performance and substrate coupling. The measured performances are 13-bit dynamic range operating at 2MS/s and 12-bit dynamic range operating at 4MS/s. The modulator consumes 77mW from a 3.3-V supply and occupies 1.32 mm2. This work has been supported by the ESPRIT Project 29261 MIXMODEST. Peer reviewed |
| URI: | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3768 |
| Other Identifiers: | The 8th IEEE International Conference on Electronics, Circuits and Systems 1: 501-504 (2001) 0-7803-7057-0 http://hdl.handle.net/10261/3768 10.1109/ICECS.2001.957788 |
| Appears in Collections: | Digital Csic |
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