Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3768
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dc.creatorRío, Rocío del-
dc.creatorRosa, José M. de la-
dc.creatorMedeiro, Fernando-
dc.creatorPérez-Verdú, Belén-
dc.creatorRodríguez-Vázquez, Ángel-
dc.date2008-04-28T05:37:33Z-
dc.date2008-04-28T05:37:33Z-
dc.date2001-09-
dc.date.accessioned2017-01-31T01:04:14Z-
dc.date.available2017-01-31T01:04:14Z-
dc.identifierThe 8th IEEE International Conference on Electronics, Circuits and Systems 1: 501-504 (2001)-
dc.identifier0-7803-7057-0-
dc.identifierhttp://hdl.handle.net/10261/3768-
dc.identifier10.1109/ICECS.2001.957788-
dc.identifier.urihttp://dspace.mediu.edu.my:8181/xmlui/handle/10261/3768-
dc.descriptionComunicación presentada al "ICECS 2001" celebrado del 2 al 5 de Septiembre del 2001 en Malta.-
dc.descriptionWe present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use only 16 oversampling ratio. Especial emphasis is placed on technology issues, namely: poor analog performance and substrate coupling. The measured performances are 13-bit dynamic range operating at 2MS/s and 12-bit dynamic range operating at 4MS/s. The modulator consumes 77mW from a 3.3-V supply and occupies 1.32 mm2.-
dc.descriptionThis work has been supported by the ESPRIT Project 29261 MIXMODEST.-
dc.descriptionPeer reviewed-
dc.format453788 bytes-
dc.formatapplication/pdf-
dc.languageeng-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.relationhttp://dx.doi.org/10.1109/ICECS.2001.957788-
dc.rightsopenAccess-
dc.subjectAnalog-to-digital converters-
dc.subjectADSL application-
dc.titleHigh-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology-
dc.typeComunicación de congreso-
Appears in Collections:Digital Csic

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