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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3744Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.creator | Medeiro, Fernando | - |
| dc.creator | Pérez-Verdú, Belén | - |
| dc.creator | Rosa, José M. de la | - |
| dc.creator | Rodríguez-Vázquez, Ángel | - |
| dc.date | 2008-04-25T10:40:04Z | - |
| dc.date | 2008-04-25T10:40:04Z | - |
| dc.date | 1997 | - |
| dc.date.accessioned | 2017-01-31T01:03:50Z | - |
| dc.date.available | 2017-01-31T01:03:50Z | - |
| dc.identifier | Journal Circuit Theory Applications 25(5): 319-334 (1997) | - |
| dc.identifier | 0098-9886 | - |
| dc.identifier | http://hdl.handle.net/10261/3744 | - |
| dc.identifier | 10.1002/(SICI)1097-007X(199709/10)25:5<319::AID-CTA976>3.0.CO;2-U | - |
| dc.identifier | 1097-007X | - |
| dc.identifier.uri | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3744 | - |
| dc.description | El pdf del artículo es la versión post-print. | - |
| dc.description | This paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16.4 bit at a digital output rate of 9.6 kHz with a power consumption of 1.7 mW. It yields a value of Power(W)/[2^resolution(bit) * Outpur rate(Hz)] which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable ΣΔMs using CAD methodologies. | - |
| dc.description | Peer reviewed | - |
| dc.format | 1635147 bytes | - |
| dc.format | application/pdf | - |
| dc.language | eng | - |
| dc.publisher | Wiley-Blackwell | - |
| dc.relation | Postprint | - |
| dc.relation | http://dx.doi.org/10.1002/(SICI)1097-007X(199709/10)25:5<319::AID-CTA976>3.0.CO;2-U | - |
| dc.rights | openAccess | - |
| dc.subject | Mixed-signal circuits | - |
| dc.subject | Data conversion | - |
| dc.subject | ΣΔM | - |
| dc.subject | Optimized design | - |
| dc.subject | CAD tools | - |
| dc.title | Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology | - |
| dc.type | Artículo | - |
| Appears in Collections: | Digital Csic | |
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