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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3730Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.creator | Río, Rocío del | - |
| dc.creator | Rosa, José M. de la | - |
| dc.creator | Pérez-Verdú, Belén | - |
| dc.creator | Delgado-Restituto, Manuel | - |
| dc.creator | Domínguez-Castro, R. | - |
| dc.creator | Medeiro, Fernando | - |
| dc.creator | Rodríguez-Vázquez, Ángel | - |
| dc.date | 2008-04-25T05:32:02Z | - |
| dc.date | 2008-04-25T05:32:02Z | - |
| dc.date | 2008-01 | - |
| dc.date.accessioned | 2017-01-31T01:03:38Z | - |
| dc.date.available | 2017-01-31T01:03:38Z | - |
| dc.identifier | IEEE Transactions on Circuits and Systems I: Regular Papers 51(1): 47-62 (2004) | - |
| dc.identifier | 1549-8328 | - |
| dc.identifier | http://hdl.handle.net/10261/3730 | - |
| dc.identifier | 10.1109/TCSI.2003.821308 | - |
| dc.identifier.uri | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3730 | - |
| dc.description | We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25μm CMOS process with metal–insulator–metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB, respectively. The ΣΔ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the ΣΔ modulator. | - |
| dc.description | This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE. | - |
| dc.description | This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE. | - |
| dc.description | Peer reviewed | - |
| dc.format | 888235 bytes | - |
| dc.format | application/pdf | - |
| dc.language | eng | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.relation | http://dx.doi.org/10.1109/TCSI.2003.821308 | - |
| dc.rights | openAccess | - |
| dc.subject | Analog-to-digital converters | - |
| dc.subject | ADSL | - |
| dc.subject | ΣΔ modulation | - |
| dc.subject | Switched-capacitor circuits | - |
| dc.title | Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+ | - |
| dc.type | Artículo | - |
| Appears in Collections: | Digital Csic | |
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