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http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3730| Title: | Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+ |
| Keywords: | Analog-to-digital converters ADSL ΣΔ modulation Switched-capacitor circuits |
| Publisher: | Institute of Electrical and Electronics Engineers |
| Description: | We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25μm CMOS process with metal–insulator–metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB, respectively. The ΣΔ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the ΣΔ modulator. This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE. This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE. Peer reviewed |
| URI: | http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3730 |
| Other Identifiers: | IEEE Transactions on Circuits and Systems I: Regular Papers 51(1): 47-62 (2004) 1549-8328 http://hdl.handle.net/10261/3730 10.1109/TCSI.2003.821308 |
| Appears in Collections: | Digital Csic |
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