A 74dB Dynamic Range, 1.1-MHz Signal Band 4th-Order 2-1-1 Cascade Multi-Bit CMOS ΣΔ Modulator for ADSL

Please use this identifier to cite or link to this item: http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3597

Full metadata record

DC Field	Value	Language
dc.creator	Medeiro, Fernando	-
dc.creator	Pérez-Verdú, Belén	-
dc.creator	Rodríguez-Vázquez, Ángel	-
dc.date	2008-04-15T17:18:25Z	-
dc.date	2008-04-15T17:18:25Z	-
dc.date	1997-09	-
dc.date.accessioned	2017-01-31T01:02:22Z	-
dc.date.available	2017-01-31T01:02:22Z	-
dc.identifier	European Solid-State Circuits Conference (ESSCIRC’97), pp. 72-75, Southampton - UK, September 16-18, 1997.	-
dc.identifier	http://hdl.handle.net/10261/3597	-
dc.identifier.uri	http://dspace.mediu.edu.my:8181/xmlui/handle/10261/3597	-
dc.description	This paper explores the use of ΣΔ techniques for A/D conversion exceeding 1-MHz signal bandwidth. A cascade modulator architecture is proposed which combines single-bit and multi-bit quantization to obtain more than 12-b Dynamic Range (DR) with an oversampling ratio of only 16, and with neither calibration nor trimming required. Measurements from a 0.7mm CMOS prototype show 74dB DR in 1.1-MHz signal band at 35.7-MHz clock rate, with a power consumption of 55mW from a 5-V supply.	-
dc.description	This work has been supported by the European Union, under ESPRIT Project 8795-AMFIS.	-
dc.description	Peer reviewed	-
dc.format	106324 bytes	-
dc.format	application/pdf	-
dc.language	eng	-
dc.rights	openAccess	-
dc.subject	ΣΔ Modulator	-
dc.subject	A/D Conversion	-
dc.subject	CMOS A/D Converter	-
dc.title	A 74dB Dynamic Range, 1.1-MHz Signal Band 4th-Order 2-1-1 Cascade Multi-Bit CMOS ΣΔ Modulator for ADSL	-
dc.type	Comunicación de congreso	-
Appears in Collections:	Digital Csic

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